1. Technical Field
The present invention relates to a nonvolatile memory apparatus, and more particularly, to a write control method of a nonvolatile memory apparatus.
2. Related Art
A useful feature of a nonvolatile memory apparatus is low power consumption, and a nonvolatile memory apparatus that does not perform a refresh operation may consume less power. A phase-change random access memory (PRAM), which is a nonvolatile memory apparatus that does not perform a refresh operation, applies an electrical pulse to a phase change layer formed of a chalcogenide compound and stores data using a resistance difference between an amorphous state and a crystal state. The phase change layer may include a chalcogenide compound such as Ge2Sb2Te5 (GST). Here, the amorphous state (or reset state) may be obtained by applying a pulse current to a memory cell during a designated time, and the crystal state (or set state) may be obtained by applying a pulse current during a longer time than the designated time.
The GST of the PRAM has its own physical characteristics, and a representative example of the physical characteristic is resistance drift. The resistance drift refers to a phenomenon where the resistance of GST, which is physically and chemically unstable, increases with time while the GST is electrically stabilized. The resistance drift becomes prominent in the amorphous state.
The resistance drift exhibits an exponential function characteristic with respect to time, and the exponential function has a random variable within the range of a designated constant, regardless of a unique characteristic of a phase-change cell.
However, when the random variable of the exponential function is significantly changed, the resistance change is increased. Accordingly, the resistance value may be increased after a constant time passes, unlike when an initial write operation is performed.
As such, when the resistance value is significantly changed after a constant time passes, the reliability of a nonvolatile memory apparatus may be reduced.